The invention relates to an arrangement, particularly an analog-digital digital-nalog converter, having a resistance line or resistance chain to which are connected respective voltage comparators having a first comparator input thereof connected at respective points along the resistance with the first comparator input in each case comprising the control electrode terminal of a transistor.
A converter of this general type is described in prior publication "High-speed A/D Converter Monolithic Techniques" in IEE CAT. N. 72 C3/IFFCC, pages 146-147 by D. R. Breuer. In the described circuit the voltage comparator comprises expensive circuits employing operational amplifiers, as a result of which a converter utilizing the same cannot be produced, without difficulties, in the form of integrated semiconductor circuits. Further, the number of voltage comparators which can be employed in a converter of this type is limited.